1. Field of the Invention
The present invention relates to physical image converting circuits, and more particularly, to physical image converting circuits used in a memory tester or an integrated circuit tester for analyzing the failure of storage devices to be measured. The data are read as the logical image from each of the corresponding storage regions to each input/output bit (I/O bit) of the storage device and are stored in each of the corresponding storage regions to each I/O bit of a memory used for failure analysis. The physical image converting circuit rapidly converts the logical image of data from the memory into a physical image so that the data corresponds to a physical position on a wafer chip of the memory.
2. Background Art
In the case of analyzing the failure of a storage device, data are read from each memory cell of the storage device to be measured and are stored as "logical images" in the corresponding storage region to addresses of a plurality of memories used for failure analysis (hereafter referred to as failure analysis memories). The plurality of the failure analysis memories is mounted on a plurality of printed circuit boards in a memory tester or an integrated circuit tester. The "logical image" will be explained with reference to FIG. 4. In FIG. 4, each failure analysis memory 7A through 7D has a storage capacity which corresponds to X addresses having a value of 0 through 3, and to Y addresses having a value of 0 or 1. The failure analysis memories 7A through 7D form a failure analysis memory 7. Each of the failure analysis memories 7A through 7D correspond to each of input/output bit data (I/O bit data) read from I/O pins 0 through 3 of the failure analysis memory 7. Therefore, when one of the combinations of X and Y addresses is supplied to the failure analysis memory 7, each 1-bit of data is read from each of the failure analysis memories 7A through 7D and thereby 4-bit data is delivered from the I/O pins 0 through 3 of the failure analysis memory 7. In FIG. 4, each fall F is stored in the corresponding storage regions of the failure analysis memories 7A and 7B to the combination of the X address 0 and the Y address 1 and of the failure analysis memories 7C and 7D to the combination of the X address 0 and the Y address 0. Accordingly, in this specification, as shown in FIG. 4, the term "logical image" visually represents the storage state where the data are the corresponding storage region to the combination of the X and Y addresses of every I/O bit in the failure analysis memory 7.
FIG. 5 shows the actual, i.e. physical, alignment of the failure analysis memories 7A through 7D in the wafer chip and the actual, i.e. physical, position on the wafer chip of the fails F stored in the failure analysis memories 7A through 7D. In FIG. 5, it can be seen that the four fails F are stored in adjacent memory cells at the center area of the failure analysis memory 7, namely, that the adjacent memory cells at each adjacent corner in the failure analysis memories 7A through 7D are defective. Therefore, the term "physical image" indicates a visual representation of the physical storage state of the data on the wafer chip of the failure analysis memory 7, into which the data of the logical image are converted so that the position of the fail F can be seen on the actual wafer chip of the failure analysis memory 7. It is indispensable for the failure analysis to convert the logical image into a physical image.
It is conventionally known to read out the data represented by the logical image from each of the failure analysis memories 7A through 7D and to convert the logical image into a physical image using software or a RAM.
An example of the structure of a conventional physical image converting circuit using a RAM will be explained with reference to FIG. 6. In FIG. 6, a counter 1, a failure analysis memory 7, a selector 8, a CPU 9, and a conversion memory 10, are provided. In FIG. 6, the conversion memory 10 is made up of a RAM and conversion output data are pre-stored in the corresponding storage region to each address therein. The conversion output data X0, X1, Y0, P0 and P1 corresponding to addresses represented by bit data A0 through A4 supplied from the counter 1 are read out from the conversion memory 10. The failure analysis memory 7 is made up of a plurality of failure analysis memories 7A through 7D. I/O bit data I/O0 through I/O3 corresponding to the bit data X0, X1, and Y0 among the conversion output data supplied from the conversion memory 10 are read out from the failure analysis memory 7. The selector 8 selects any one of I/O bit data I/O0 through I/O3 supplied from the failure analysis memory 7 based on the data P0 and P1 from the conversion memory 10 and supplies the selected data to the CPU 9. Accordingly, the data stored as the logical image in the failure analysis memory 7 are sequentially expanded and are converted into the physical image.
Next, the operation of the physical image converting circuit shown in FIG. 6 will be explained with reference to FIGS. 7 through 9. FIG. 7 shows the physical alignment of memory cells in the failure analysis memory 7 in the case where the failure analysis memory 7 shown in FIG. 4 is made up of four failure analysis memories 7A through 7D. In FIG. 7, the I/O bit data I/O0 are stored in the upper left part of the failure analysis memory 7, the I/O bit data I/O1 are stored in the upper right part thereof, the I/O bit data I/O2 are stored in the lower left part thereof and the I/O bit data I/O3 are stored in the lower right part thereof. In FIG. 7, the order of X addresses are reversed to the logical image in each of the storage regions of the I/O bit data I/O0 and I/O2. FIG. 8 shows the numbered memory cells of the failure analysis memory 7 in the case of the physical alignment of the memory cells shown in FIG. 7. In FIG. 8, there are thirty-two memory cells in the failure analysis memory 7 and the data are read out from the memory cells as a physical image from 1to 32 in numerical order.
FIG. 9 shows an example of the data stored in the conversion memory 10. In FIG. 9, the addresses consist of the bit data A0 through A4 of 5 bits and conversion output data are stored in the corresponding storage region to each address of the conversion memory 10. In FIG. 9, as an example of the conversion output data, 2-bits data (P0, P1) for determining any I/O bit data among the I/O bit data I/O0 through I/O3 in the selector 8, 1-bit data Y0 indicating the Y address 0 or 1 of each of the memory cell of the failure analysis memory 7, and 2-bit data (X0, X1) indicating the X addresses 0 through 3 of each of the memory cell of the failure analysis memory 7, are shown. When the bit data (P0, P1) is "00", the selection of the I/O bit data I/O0 is instructed to the selector 8. When the data (P0, P1) is "01", the selection of the I/O bit data I/O1 is instructed to the selector 8. When the data (P0, P1) is "10", the selection of the I/O bit data I/O2 is instructed to the selector 8. In addition, when the data (P0, P1) is "11", the selection of the I/O bit data I/O3 is instructed to the selector 8.
For example, when "00000" is supplied as an address to the conversion memory 10, "00" is delivered as the bit data (P0, P1), "0" is delivered as the bit data Y0, that is, "0" is delivered as the Y address, and "11" is delivered as the bit data (X0, X1), that is, "3" is delivered as the X address from the conversion memory 10.
As explained above, by storing the conversion output data in the corresponding storage region in each address of the conversion memory 10 and supplying the count value generated in the counter 1 as the address to the conversion memory 10, the data can be read out from each memory cell of the failure analysis memory 7 as the physical image, from 1to 32, in numerical order as shown in FIG. 8.
Recently, since the storage capacity of the memory devices tends to be large and the cell construction of the memory devices tends to be complex, the acceleration of the failure analysis function is demanded for a memory tester or an integrated circuit tester.
However, in the case of the conversion of a logical image into a physical image using software, a very long execution time is needed.
In the case of the conversion of the logical image into the physical image using a RAM, since time for storing the conversion output data in the conversion memory 10 is needed, the larger storage capacity of the memory devices, the larger storage capacity of the conversion memory 10. In addition, in the case of increasing readout speed for reading out the conversion output data from the conversion memory 10, since high-speed access of the conversion memory 10 is necessary, the high cost of the physical image converting circuit is a drawback.